microSPARC

Jump to content
From Wikipedia, the free encyclopedia
(Redirected from MicroSPARC IIep)
microSPARC
General information
Launched1992
Discontinued1994
Designed bySun Microsystems
Performance
Max. CPU clock rate40 MHz to 125 MHz
Architecture and classification
Instruction setSPARC V8
Physical specifications
Cores
  • 1

The microSPARC (code-named Tsunami) is a discontinued microprocessor implementing the SPARC V8 instruction set architecture (ISA), developed by Sun Microsystems. It is a low-end microprocessor intended for low-end workstations and embedded systems. The microprocessor was developed by Sun, but the floating-point unit (FPU) was licensed from Meiko Scientific. It contains 800,000 transistors. It was used in the SPARCclassic and SPARCstation LX among others.

There are two variants of the microSPARC-II (code-named Swift): the microSPARC-II and microSPARC-IIep. The microSPARC-II is used in the SPARCstation 5. The microSPARC-IIep is a 100 MHz microSPARC-II with an integrated PCI controller for embedded systems. It was developed and fabricated by LSI Logic for Sun, and used in their JavaStation Network Computer.

Name (codename)ModelFrequency (MHz)Arch. versionYearTotal threads[1]Process (μm)Transistors (millions)Die size (mm²)IO PinsPower (W)Voltage (V)L1 Dcache (k)L1 Icache (k)L2 Cache (k)L3 Cache (k)
microSPARC I (Tsunami)TI TMS390S10 / TMX390S1040–50V819921×1=10.80.8225?2882.5524nonenone
microSPARC II (Swift)Fujitsu MB86904 / Sun STP101260–125V819941×1=10.52.323332153.3816nonenone

References

[edit]
  1. ^ Threads per core × number of cores
  • Sun Microsystems, Inc. (10 August 1992). "Highly Integrated SPARC Processor Implementation (Tsunami)". Hot Chips presentation.'
    microSPARC
    General information
    Launched1992
    Discontinued1994
    Designed bySun Microsystems
    Performance
    Max. CPU clock rate40 MHz to 125 MHz
    Architecture and classification
    Instruction setSPARC V8
    Physical specifications
    Cores
    • 1

    The microSPARC (code-named Tsunami) is a discontinued microprocessor implementing the SPARC V8 instruction set architecture (ISA), developed by Sun Microsystems. It is a low-end microprocessor intended for low-end workstations and embedded systems. The microprocessor was developed by Sun, but the floating-point unit (FPU) was licensed from Meiko Scientific. It contains 800,000 transistors. It was used in the SPARCclassic and SPARCstation LX among others.

    There are two variants of the microSPARC-II (code-named Swift): the microSPARC-II and microSPARC-IIep. The microSPARC-II is used in the SPARCstation 5. The microSPARC-IIep is a 100 MHz microSPARC-II with an integrated PCI controller for embedded systems. It was developed and fabricated by LSI Logic for Sun, and used in their JavaStation Network Computer.

    Name (codename)ModelFrequency (MHz)Arch. versionYearTotal threads[1]Process (μm)Transistors (millions)Die size (mm²)IO PinsPower (W)Voltage (V)L1 Dcache (k)L1 Icache (k)L2 Cache (k)L3 Cache (k)
    microSPARC I (Tsunami)TI TMS390S10 / TMX390S1040–50V819921×1=10.80.8225?2882.5524nonenone
    microSPARC II (Swift)Fujitsu MB86904 / Sun STP101260–125V819941×1=10.52.323332153.3816nonenone

    References

    1. ^ Threads per core × number of cores
    • Sun Microsystems, Inc. (10 August 1992). "Highly Integrated SPARC Processor Implementation (Tsunami)". Hot Chips presentation.'
    Retrieved from "https://en.wikipedia.org/w/index.php?title=MicroSPARC&oldid=1285966462"